Method and system for performing memory repair analysis
US6751760B2 · kind B2 · utility
2Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.