Systems and methods for testing a memory
US6751762B2 · kind B2 · utility
6Cited by
6References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for testing a memory array in an integrated circuit. The method provides a favorable tradeoff between test time and quality of test results, by compressing data in a time direction, but not compressing results from multiple primary data lines corresponding to respective I/O pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.