Method for assembling integrated circuits with protection of the circuits against electrostatic discharge
US6753204B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and a circuit arrangement for protecting integrated circuits against electrostatic discharge (ESD) during and after packaging. An electrical connection between two integrated circuits is made by producing a low-impedance connection in the first integrated circuit, between a signal pad and a pad for a supply potential. The connection has a portion of reduced cross section, which is preferably severed by a current pulse applied after the arrangement has been assembled in a package and the connection has been electrically bonded to the second integrated circuit. The ESD protection during assembly requires no additional chip surface area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.