Method of forming a gate structure
US6753225B1 · kind B1 · utility
0Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2003 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate structure. A substrate having thereon at least one stacked gate is provided. The stacked gate has a gate insulating layer, a polysilicon layer, a silicate layer, and a cap layer. A sacrificial layer is deposited on the substrate, and etched backed to expose the cap layer and an upper portion of the silicate layer. Then, the exposed silicate layer is partially removed to form a recess. The recess is filled with silicon nitride. Finally, a spacer is formed on walls of the stacked gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.