Integration scheme for dual damascene structure
US6753258B1 · kind B1 · utility
18Cited by
25References
60Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Feb 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for processing a substrate to form a feature in low k dielectric materials. One aspect of the invention provides a method for processing a substrate including forming a feature definition in a dielectric material deposited on a surface of a substrate, depositing one or more conductive materials to fill at least a portion of the feature definition, planarizing the substrate surface to expose the dielectric material, removing at least a portion of the dielectric material, and depositing a low k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.