Transistor having improved gate structure
US6753559B2 · kind B2 · utility
1Cited by
17References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.