Structure of a substrate for a high density semiconductor package
US6753600B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2003 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure of a substrate for a high-density semiconductor package is provided. The structure of the substrate comprises a metal substrate and an interconnect substrate disposed on the second surface of the metal substrate. The interconnect substrate comprises at least one or more metal and inter-metal dielectric layers comprising a plurality of traces/lines, pads and vias appropriate for the design. One or more dice are attached to the top surface of the metal substrate, wire bonds are used to connect the dice through open slots on the metal substrate to the Ni/Au plated pads on the interconnect substrate. The uppermost wiring layers are electrically connected to the ball pads on the bottom surface through a plurality of wiring layers and conductive vias. The ball pads are attached to the lowest wiring layer. At least one thermally conductive via is attached to the metal substrate underneath the metal die pad and in direct physical contact so that the heat generated by the IC chip can be efficiently conducted and transferred to the PCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.