Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory
US6754106B1 · kind B1 · utility
19Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.