Test of a semiconductor memory having a plurality of memory banks

US6754116B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Janik · Hersbruck, DE
• Sebastian Kuhne · Radebeul, DE

Key dates

• Filing date: Jul 18, 2002
• Grant date: Jun 22, 2004
• Expiry date: Jul 18, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/26
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands, each for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.