Hybrid MRAM array structure and operation
US6754124B2 · kind B2 · utility
31Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.