Reduced latency wide-I/O burst architecture
US6754135B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 2002 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Nov 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls. For every I/O, eight bits of data are presented to a 9-to-1 multiplexer. The first of eight bits in the burst sequence is the access time-limiting bit and is preselected by the burst base addresses of the 9-to-1 multiplexer. Subsequent bits in the burst sequence have extra half-cycles to be output, and use look-aside 8-to-1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.