Data processing apparatus with indirect register file access
US6754809B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2000 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Oct 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.