Algorithm for non-volatile memory updates
US6754828B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1999 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Jul 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM.The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is used to call a specific non-volatile memory implementation routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.