Semiconductor test system having double data rate pin scrambling
US6754868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Nov 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.