Simplified twin monos fabrication method with three extra masks to standard CMOS
US6756271B1 · kind B1 · utility
30Cited by
6References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2003 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Mar 12, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.