Method for minimizing product turn-around time for making semiconductor permanent store ROM cell

US6756275B1 · kind B1 · utility

Assignee

• Faraday Technology Corp. · TW

Inventors

• Kwo-Jen Liu · San Jose, US
• Chih-Hung Chen
• An-Ru Cheng · Valencia, US

Key dates

• Filing date: Mar 28, 2003
• Grant date: Jun 29, 2004
• Expiry date: Mar 28, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an “ON” state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic “OFF” state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.