Method for hardening gate oxides using gate etch process
US6756291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation including providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.