Optimized-delay multiplexer
US6756820B1 · kind B1 · utility
6Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1999 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | May 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.