Sigma-delta programming device for a PLL frequency synthesizer, configuration using the sigma-delta programming device, PLL frequency device, and method for programming a programmable device

US6756927B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Markus Hammes · Dinslaken, DE
• Stefan Waasen · Sollentuna, SE

Key dates

• Filing date: Aug 5, 2003
• Grant date: Jun 29, 2004
• Expiry date: Aug 5, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/1976
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A sigma-delta programmer is supplied with a data word having a word length of N bits. The most significant L bits of the data word represent the places before the decimal point, and the remaining N−L less significant bits represent the places after the decimal point in the data word. A sigma-delta modulator is supplied with the N−L+1 less significant bits of the data word. An adder receives the L−1 most significant bits of the data word and a data word that is output by the sigma-delta modulator, and outputs a signal, which is multiplied by the value two by a multiplier.