Adaptive cache coherence protocols
US6757787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Jun 29, 2004 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of “mandatory” rules and a second subset of “voluntary” rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.