Stitch and select implementation in twin MONOS array

US6759290B2 · kind B2 · utility

Assignee

• Halo LSI, Inc. · US

Inventors

• Tomoko Ogura · New York, US
• Tomoya Saito · Tokyo, JP
• Seiki Ogura · Wappingers Falls, US
• Kimihiro Satoh · Wilsonville, US

Key dates

• Filing date: Mar 26, 2002
• Grant date: Jul 6, 2004
• Expiry date: May 16, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.