Method of etching a trench in a silicon-on-insulator (SOI) structure
US6759340B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 9, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30655
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.