Method of avoiding dielectric arcing
US6759342B2 · kind B2 · utility
2Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/3342
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.