SiC semiconductor device
US6759684B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 14, 2001 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Nov 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
Abstract
An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.