Voltage controlled oscillation circuit
US6759875B2 · kind B2 · utility
17Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.