Combined floating-point logic core and frame buffer
US6760033B2 · kind B2 · utility
4Cited by
16References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jan 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.