Semiconductor memory device capable of generating internal data read timing precisely
US6760269B2 · kind B2 · utility
212Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | May 27, 2003 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.