Method of photolithographically forming extremely narrow transistor gate elements
US6762130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | May 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.