Inventor · Sachse, TX, US

Jarvis Benjamin Jacobs

21Patents
4h-index
25Co-inventors
63Inventor score

Filing activity: Mar 7, 1997 → Jan 24, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US5936278A Semiconductor on silicon (SOI) transistor with a halo implant Electricity 47 Expired
US6866974B2 Semiconductor process using delay-compensated exposure Physics 13 Expired
US6583013B1 Method for forming a mixed voltage circuit having complementary devices Electricity 10 Expired
US6762130B2 Method of photolithographically forming extremely narrow transistor gate elements Electricity 9 Expired
US9431286B1 Deep trench with self-aligned sinker Electricity 4 Active
US7562333B2 Method and process for generating an optical proximity correction model based on layout density Physics 4 Active
US9401410B2 Poly sandwich for deep trench fill Electricity 3 Active
US8802577B2 Method for manufacturing a semiconductor device using a nitrogen containing oxide layer Electricity 2 Active
US7560779B2 Method for forming a mixed voltage circuit having complementary devices Electricity 1 Expired
US7569464B2 Method for manufacturing a semiconductor device having improved across chip implant uniformity Electricity 1 Active
US9741718B2 High voltage CMOS with triple gate oxide Electricity 1 Active
US9117687B2 High voltage CMOS with triple gate oxide Electricity 0 Active
US11121207B2 Integrated trench capacitor with top plate having reduced voids Electricity 0 Active
US9583579B2 Poly sandwich for deep trench fill Electricity 0 Active
US12015057B2 Carbon, nitrogen and/or fluorine co-implants for low resistance transistors Electricity 0 Active
US9865691B2 Poly sandwich for deep trench fill Electricity 0 Active
US10566200B2 Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings Electricity 0 Active
US10714474B2 High voltage CMOS with triple gate oxide Electricity 0 Active
US8828855B2 Transistor performance using a two-step damage anneal Electricity 0 Active
US9029251B2 Transistor performance using a two-step damage anneal Electricity 0 Active
US9054056B2 Transistor performance using a two-step damage anneal Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.