Light thin stacked package semiconductor device and process for fabrication thereof
US6762488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked package semiconductor device includes a semiconductor chip package, which has been reduced in thickness through a polishing after being sealed in a resin package, and a semiconductor flip chip electrically connected to the semiconductor chip package through conductive bumps embedded in an underfill resin layer below the semiconductor flip chip; the semiconductor chip package is stacked with the semiconductor flip chip, and the semiconductor flip chip is reduced in thickness through the polishing after the resultant structure is molded in a synthetic resin package; although the semiconductor chip package and semiconductor flip chip are reduced in thickness, the polishing is carried out after the semiconductor chip are sealed in the resin so that the semiconductor chips are less broken during the polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.