Ball grid array package for high speed devices
US6762498B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jul 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09718
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate (300) for use in semiconductor devices, having first (301a) and second (301b) surfaces and a base structure including insulating material. A plurality of I/O terminal pads (302, 303) is distributed on the first and second surfaces, respectively, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers (304 to 309) is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer (304 or 307, respectively) opposite each of the surfaces has openings (320a, 320b) therein configured so that the metal areas (307a) directly opposite each of the terminal pads (303) are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals (303) and the remainder of the metal layer (307).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.