Semiconductor integrated circuit tester
US6762599B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit tester includes a housing having a tester interface area, a guide structure in the housing and defining an engagement axis that intersects the tester interface area, and a circuit board structure fitted in the guide structure in a manner allowing movement of the circuit board structure relative to the housing along the engagement axis. The circuit board structure has a tester interface that is exposed exteriorly of the housing at the tester interface area. An attachment mechanism releasably engages a test board having a test board interface and secures the test board against movement along the engagement axis in a direction away from the tester interface area. When the test board is secured to the housing by the attachment mechanism and the tester interface is not engaged with the test board interface, the circuit board structure may be urged to move along the engagement axis to force the tester interface into engagement with the test board interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.