VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors
US6762629B2 · kind B2 · utility
67Cited by
38References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.