Low clock swing latch for dual-supply voltage design
US6762957B2 · kind B2 · utility
11Cited by
16References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.