Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor
US6762966B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.