Wafer thinning techniques
US6764573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2001 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67346
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatuses (10, 100), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses (10, 100) include a fixture (12, 102) having a plurality of horizontal receptacles (14, 16, 18, 20, 104, 106, 108, 110) for receiving the semiconductor wafers (W). The loaded fixtures (12, 102) are then immersed into an etchant solution (36, 146) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution (36, 146) is preferably heated to about 40° C.-50° C. and constantly stirred with a magnetic stirring bar (48, 158). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution (36, 146). The apparatuses (10, 100) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.