Device and method of low voltage SCR protection for high voltage failsafe ESD applications
US6764892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2003 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/80
Abstract
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.