Field effect transistor and fabrication method

US6765248B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Tobben · Fishkill, US
• Thomas Schuster · Ottenbach, DE

Key dates

• Filing date: Nov 25, 2002
• Grant date: Jul 20, 2004
• Expiry date: Dec 4, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.