Dynamic delay line control
US6765419B2 · kind B2 · utility
2Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | May 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.