Duty-cycle correction circuit
US6765421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.