Semiconductor memory device having a main word-line layer disposed above a column selection line layer
US6765815B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a semiconductor memory device having a multilevel interconnection structure with no conventional limitation on the number of lines. The semiconductor memory device has a multilevel interconnection structure in which column selection lines extending in the Y direction and main word lines extending in the X direction are arranged in different layers. The layer including the column selection lines is disposed under the layer including the main word lines. In the structure, in sub-word driver areas intersecting the X direction, the main word lines are arranged in a top layer and sub-word selection lines are arranged in a layer lower than the top layer. The lower layer includes a pattern of islands. According to this interconnection structure, the number of islands can be reduced. Consequently, a plurality of power lines can be arranged between the adjacent main word lines in the sub-word driver areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.