Predictive processing method in a semiconductor processing facility
US6766285B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Wafer processing cycle times are substantially reduced by predicting and correcting downstream processing location anomalies before a wafer lot is released to the next processing location on the processing line. In an example embodiment, a method of verifying downstream processing line readiness in a semiconductor processing facility having a material handling system includes presenting a wafer lot to a first application processing location. A signal is then sent to a second application processing location to verify readiness by simulating the second application processing on the wafer lot. The availability or operating status of the second processing location is then communicated to the material handling system, the material handling system communicating instructions to the first processing location on where to send the wafer lot after the processing simulation is complete. The readiness verification method is repeated until the wafer lot is completely processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.