Microprocessor with conditional cross path stall to minimize CPU cycle time length
US6766440B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.