Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
US6766442B1 · kind B1 · utility
42Cited by
20References
3Claims
0Family size
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Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions, a condition register, and a branch prediction circuit that predicts a condition register-dependent branch instruction by reference to a potentially stale condition register value to produce a speculative instruction fetch address. In a preferred embodiment, the processor includes branch execution circuitry that subsequently determines if the speculative instruction fetch address is correct by reference to a non-stale value of the condition register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.