Mask/wafer control structure and algorithm for placement

US6766507B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James A. Bruce · Williston, US
• Stephen E. Knight · South Burlington, US
• Joshua J. Krueger · Burlington, US
• Matthew Nicholls · Pleasant Valley, US
• Jed H. Rankin · South Burlington, US

Key dates

• Filing date: Apr 12, 2002
• Grant date: Jul 20, 2004
• Expiry date: Jun 15, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F7/70683
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.