Method of manufacturing semiconductor device
US6767826B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/522
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first insulating layer is formed on first wiring and thereafter an etching resistant film is formed thereon. A lower layer portion of a second insulating layer is formed on the etching resistant film. Upon etching for forming dummy trenches, the rate of etching of the etching resistant film is less than or equal to one-tenth the rate of etching of the insulating layer. Therefore, the etching resistant film functions as an etching stopper and the etching thereof does not proceed to the first insulating layer. Thus, the interval between the corresponding first wiring and a second wiring can be reliably maintained and an increase in parasitic capacitance is hence prevented. An insulator lying within a wiring section is made unnecessary while a dishing phenomenon is prevented, by bottom-up filling of a copper-plated film due to the dummy trenches. Thus, wiring resistance is prevented from increasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.