Structure and method of making three finger folded field effect transistors having shared junctions
US6768143B1 · kind B1 · utility
6Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.