Hoki Kim
29Patents
8h-index
32Co-inventors
71Inventor score
Filing activity: Nov 30, 2001 → Jul 26, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7145829B1 | Single cycle refresh of multi-port dynamic random access memory (DRAM) | Physics | 29 | Expired |
| US7714326B2 | Electrical antifuse with integrated sensor | Electricity | 23 | Active |
| US6990025B2 | Multi-port memory architecture | Physics | 18 | Expired |
| US6891389B1 | System and method for detecting quiescent current in an integrated circuit | Physics | 18 | Expired |
| US7046565B1 | Bi-mode sense amplifier with dual utilization of the reference cells and dual precharge scheme for improving data retention | Physics | 12 | Expired |
| US6954387B2 | Dynamic random access memory with smart refresh scheduler | Physics | 12 | Expired |
| US7286437B2 | Three dimensional twisted bitline architecture for multi-port memory | Electricity | 9 | Expired |
| US6950353B1 | Cell data margin test with dummy cell | Physics | 8 | Expired |
| US7440353B2 | Floating body control in SOI DRAM | Physics | 8 | Active |
| US9972609B2 | Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor | Electricity | 7 | Active |
| US8994402B2 | Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit | Electricity | 6 | Active |
| US6768143B1 | Structure and method of making three finger folded field effect transistors having shared junctions | Physics | 6 | Expired |
| US6947348B2 | Gain cell memory having read cycle interlock | Physics | 5 | Expired |
| US7885138B2 | Three dimensional twisted bitline architecture for multi-port memory | Physics | 5 | Active |
| US7046572B2 | Low power manager for standby operation of memory system | Physics | 5 | Expired |
| US10354976B2 | Dies-on-package devices and methods therefor | Electricity | 4 | Active |
| US9991233B2 | Package-on-package devices with same level WLP components and methods therefor | Electricity | 4 | Active |
| US8816720B2 | Single power supply logic level shifter circuit | Physics | 4 | Active |
| US9991235B2 | Package on-package devices with upper RDL of WLPS and methods therefor | Electricity | 4 | Active |
| US7136317B1 | DRAM with self-resetting data path for reduced power consumption | Physics | 4 | Expired |
| US7668003B2 | Dynamic random access memory circuit, design structure and method | Electricity | 3 | Active |
| US7023758B2 | Low power manager for standby operation of a memory system | Physics | 3 | Expired |
| US6816397B1 | Bi-directional read write data structure and method for memory | Physics | 2 | Expired |
| US7596038B2 | Floating body control in SOI DRAM | Physics | 2 | Active |
| US9985007B2 | Package on-package devices with multiple levels and methods therefor | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.