Complementary MOS transistors having p-type gate electrodes
US6768174B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A complementary MOS semiconductor device is provided which is manufactured at low cost and in a short manufacturing period, which enables low voltage operation, and has low power consumption and high driving capability, and which can realizes a power management semiconductor device or an analog semiconductor device at high speed operation. A gate electrode of a CMOS is formed of p-type polycrystalline silicon of a singe polarity or a p-type polycide structure. A PMOS is of surface channel type, and thus, enables a shorter channel and a lower threshold voltage. Also, an NMOS of buried channel type has an extremely shallow buried channel since arsenic having a small diffusion coefficient is used as an impurity for threshold control in the NMOS, and thus, enables a shorter channel and a lower threshold voltage. Further, a resistor used in a voltage dividing circuit or a CR circuit is comprised of polycrystalline silicon different from that for the gate electrode, and thus, a voltage dividing circuit with high precision is provided. Accordingly, the high-speed power management semiconductor device or analog semiconductor device is realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.