Circuit and method for reducing power usage in a content addressable memory
US6768659B2 · kind B2 · utility
38Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) including a plurality of rows, each of the rows has a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.